Physical Verification Tools In Design Process Includes
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on "Design Using CAD Tools".
1. Physical verification tools in design process include
a) circuit extractors
b) textual entry
c) graphical entry
d) simulation
View Answer
Answer: a
Explanation: Physical verification tools in design process includes design rule checking, circuit extractors, ratio rule and other static checks.
2. Behavioral tools contain
a) graphical entry
b) design check
c) performance check
d) simulation
View Answer
Answer: d
Explanation: Behavioral tools contain simulation at various levels. It will be required to check out the design before turning out the design in silicon.
3. Simulators are available for
a) transistor level logic
b) switch level logic
c) gate level logic
d) design level logic
View Answer
Answer: b
Explanation: Simulators are available for switch level logic and timing simulation. This is used to check out the design.
4. Selection and placement is done using
a) cursor
b) shapes
c) textual
d) graphical
View Answer
Answer: a
Explanation: Selection and placement geometric shapes are done using some form of cursor and it may also allow selection of menu items.
5. Cursor position is controlled using
a) mouse
b) bitpad digitizer
c) mouse and bitpad digitizer
d) keyboard
View Answer
Answer: c
Explanation: Positioning of cursor may be affected from keyboard and cursor position is controlled from a bitpad digitizer or a mouse.
6. CIF code is a ______ layout language.
a) mask level
b) floor level
c) design level
d) transistor level
View Answer
Answer: a
Explanation: CIF is an example of mask level layout language, which are well suited to physical layout description but not for capturing the design intent.
7. Which verification capture's design intent and not physical layout?
a) mask level layout language
b) transistor level layout language
c) circuit description language
d) switch level layout language
View Answer
Answer: c
Explanation: Circuit description language where the primitives are circuit elements such as transistors, wires and nodes. It captures the design intent and not directly the physical layout.
8. All possible errors in mask layout can be eliminated after mask making proceeds.
a) true
b) false
View Answer
Answer: b
Explanation: The cost in time and the facilities in mask-making is such that all the possible errors must be eliminated before mask making proceeds.
9. The nature of physical layout verification software depends on
a) absolute design rules
b) fixed layout
c) virtual grid layout
d) all of the mentioned
View Answer
Answer: d
Explanation: The nature of physical layout verification design rule checking software depends on whether the design rules are absolute or lambda-based or on whether or not the layout is on a fixed or virtual grid.
10. Which is used to interpret physical layout in circuit terms?
a) circuit converter
b) layout converter
c) circuit extractor
d) layout extractor
View Answer
Answer: c
Explanation: Circuit extractor is used to convert the design information which is in the form of physical layout data to circuit terms.
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Physical Verification Tools In Design Process Includes
Source: https://www.sanfoundry.com/vlsi-questions-answers-design-using-cad-tools/#:~:text=Explanation%3A%20Physical%20verification%20tools%20in,rule%20and%20other%20static%20checks.&text=Explanation%3A%20Behavioral%20tools%20contain%20simulation,out%20the%20design%20in%20silicon.
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